1. Field of the Invention
The present invention relates generally to programmable logic array devices, and more specifically, to logic storage element architecture which permits the selective implementation of a number of different types of logic storage functions from a storage element circuit including a basic flip-flop element.
2. Description of the Prior Art
Programmable logic arrays and similar circuit elements such as programmable array logic devices have been in existence for many years. For the most part, these devices are built using an architecture which consists of an AND array in combination with an OR-arry. This combined array is in turn connected to an arbitrary number of storage elements, usually consisting of D-type flip-flops or, less frequently, JK-type flip-flops, with the outputs of these flip-flops being fed back to the input array. The output pins of such devices may be connected to either or both of the storage elements and the array. Such architecture, which is the design most commonly found in user-programmable logic devices of the type including the present invention, permits the relatively straightforward implementation of synchronous state machines, including counters and certain types of controllers.
Two main implementations of this type of architecture have appeared in recent years. The first involves the use of a D-type flip-flop whose inputs consist of an input from the OR array and a clock pulse, with both of these inputs being connected directly to the flip-flop itself. Such design has been improved upon by a routing of the signal from the OR array into an exclusive-OR gate which has an invert signal as its second input. This exclusive-OR gate's output is then routed to the D input of a D-type flip-flop and the clock pulse provides the second input. In both architectures, the output of the flip-flop is normally routed both to the output pads of the device itself and to a feedback bus which reconnects it to the AND array.
The first design mentioned above, involving the direct connection of the input signal from the OR array into the flip-flop, has an important and troublesome restriction; namely, the logical expressions which form the input to such devices must be represented in the "sum-of-products" form so that they can be implemented in the AND-OR array. This requirement results in highly inefficient representations of some logical expressions, with the attendant problem of a proliferation of signal lines in the AND array. For example, if the flip-flop in question were to be logically driven by the equation: EQU f=A.sym.B.sym.C,
where .sym. is the exclusive-OR operator, four lines in the AND array would be required. This is because the right side of the above equation, translated into the sum-of-products form, becomes: EQU f=ABC+A'B'C+A'BC'+AB'C',
where the prime indicator (as in A') indicates the inverse of the signal preceding it and ABC is the product (or logical AND) of inputs A, B and C.
This proliferation of AND array signals becomes quite problematic when some classes of expression are required as inputs to the flip-flop. For example, if the input desired is represented by the equation: EQU g=(A+B+C)(D+E+F)(G+H+I),
the expanded equation using the sum-of-products method produces 27 product terms, meaning that 27 lines will be required in the AND array; an inefficiently high number for a single input factor. The 27 product terms for the above equation in sum-of-products equivalent form are: EQU g=ADG+ADH+ADI+AEG+AEH+AEI+AFG+AFH+AFI EQU +BDG+BDH+BDI+BEG+BEH+BEI+BFG+BFH+BFI EQU +CDG+CDH+CDI+CEG+CEH+CEI+CFG+CFH+CFI
Some manufacturers have overcome this limitation of AND-OR arrays by introducing programmable inverters between the OR array and the storage element. In such embodiments, each programmable inverter is in turn composed of an exclusive-OR gate and an inversion control input supplied by a programmable fuse, or a bit from an EPROM, EEPROM, RAM or other logic-level storage device. As a result of the use of such programmable inverters, complex logic expressions which would otherwise generate an unacceptably large number of product terms ("p-terms") in the sum-of-products method described earlier, generate a manageable number when they are inverted. For example, the equation above, which generated 27 p-terms in its uninverted form, generates only three-terms when inverted; namely, EQU g'=A'B'C'+D'E'F'+G'H'I'.
Clearly, this approach represents a significant improvement over the older methods of programmable logic device architecture. There remain, however, certain types of expressions which will require a large number of p-terms regardless of whether they are expressed in non-inverted or inverted form. A classic example of such an expression is one widely used in defining synchronous binary counter circuits; i.e., EQU D4=(Q1Q2Q3).sym.Q4,
where D4 is applied to the input of a storage element, and Q4 is that element's output (also referred to as its "register feedback"). As the following two equations show, this expression generates four p-terms whether it is inverted or not: EQU D4=Q1Q2Q3Q4'+Q1'Q4+Q2'Q4+Q3'Q4 EQU D4'=Q1Q2Q3Q4+Q1'Q4'+Q2'Q4'+Q3'Q4'
Obviously, such equations are not implemented more efficiently using the programmable inverter approach to programmable logic architecture described above.